Field of the Invention
The present invention relates to an image processing apparatus, a method of controlling the same, and storage medium.
Description of the Related Art
Demand for reducing electric power consumption in image forming apparatuses has been growing. Reducing electric power consumption during standby by reducing from what is normal the electric power supply to a main controller of an apparatus when the apparatus is in a non-operating state is performed as a counter-measure for this demand. Such a power saving state in which the electric power consumption is reduced is generally referred to as a sleep mode. There are cases in which such a sleep mode is treated as a powered off state of the apparatus due to the spread of a soft switch (a switch that is controlled indirectly via a controller IC rather than being controlled by the turning on and turning off of the electric power supply by a hardware switch).
Meanwhile, in the main controller of such an apparatus, generally DRAM is used. With DRAM, it is necessary to maintain data held in the DRAM with a periodic energization referred to as a refresh. It is necessary to reconstruct data of a DRAM upon recovery from a sleep mode when the data held in the DRAM is lost during the sleep mode, and so a lot of time is required for the recovery from the sleep mode. In order to reduce such time, a self-refresh for maintaining the data of the DRAM by periodically energizing at a DRAM energization interval (a refresh cycle) that is as long as possible is used during the period from when the apparatus shifts to the sleep mode until when the apparatus recovers from the sleep mode.
The electric power consumption amount when energizing in the DRAM self-refresh has come to be considered to be a negligible amount out of the electric power consumption amount consumed in the sleep mode. However, the size of the DRAM mounted has been increasing and so the electric power consumption amount due to self-refreshing of the DRAM has come to no longer be negligible due to the reduction of the electric power consumption of parts of the apparatus other than the DRAM.
U.S. Pat. No. 8,082,387 discloses a technique for reducing electric power consumed in a memory refresh by dividing the memory, which is managed by an OS, into a plurality of blocks, and stopping refreshing of blocks to which memory segments are not allocated.
With the above described conventional example, because the memory managed by the OS is managed divided into the plurality of blocks, a sufficient power saving effect cannot be achieved when the technique is applied in a case of an image processing apparatus having a plurality of functions such as, for example, a multi function peripheral.